Unaligned accesses are forbidden in many high-performance architectures. In most of these architectures, the least ...

Nowadays it is not possible to neglect the delay of interconnection lines. The die size is rising very fast, and the delay ...

En este trabajo se propone una práctica de laboratorio para la asignatura Estructura de Computadores de primer curso de ...

In this paper, we present a model, Internode, that unifies the gate functional behavior and the dynamic one. It is based ...

En este proyecto de innovación docente se pretende profundizar en el conocimiento de la base teórica, la construcción de ...

As delay models used in logic timing simulation become more and more complex, the problem of model parameter values ...

This paper proposes a VHDL coding technique that allows for the automatic synthesis of digital circuits using the so called ...

In this work, we present the building of two well-known membrane com- puters (squares generator and divisor test). Although ...

In previous papers we have presented a very accurate model that handles the generation and propagation of glitches, which ...

The verification of the timing requirements of large VLSI circuits is generally performed by using simulation or timing ...